1. Field of the Invention
The present invention relates to an electrically erasable programmable read-only memory device, and more particularly to an improved system for driving the data-writing section of the memory device.
2. Description of the Related Art
Electrically erasable programmable read-only memories (EEPROMs) of various types, each having a large storage capacity, are known. Among these is a NAND-type flash EEPROM whose memory cells occupy a very small area.
FIG. 1 is a circuit diagram showing some of the multi-layered memory cells incorporated in a conventional NAND-type flash EEPROM. These multi-layered memory cells are arranged in n rows and two columns in a substrate W. The multi-layered memory cells forming each column are connected in series and controlled by control gates CG1, CG2, . . . CGn. The drain D of one endmost memory cell of each column is connected to the select gate SG1 of a select transistor which functions as a transfer transistor. The source S of the other endmost memory cell of each column is connected to the select gate SG2 of a select transistor which functions as a transfer transistor.
FIG. 2 is a table representing the data-writing voltages, data-reading voltages and data-erasing voltages which are applied at various points in the conventional NAND-type flash EEPROM. With reference to FIG. 2 it will be explained how data is erased from the NAND-type flash EEPROM, how data is written thereinto, and how data is read therefrom.
To erase data in the NAND-type flash EEPROM, an erase voltage V.sub.EE of 20 V is applied to the substrate W and the select gates SG1 and SG2, and the control gates CG1 to CGn are biased to 0 V. Electrons are thereby extracted from the floating gates of all memory cells. As a result, all memory cells are set into a normally-on state at a time, by a of tunnel effect of the oxide film (tunnel oxide film) formed on the substrate W. That is, every memory cell is set into a depleted state to store data "1."
To write data into the NAND-type flash EEPROM, a write voltage Vpp of 20 V is applied to the control gate of any memory cell selected, and a voltage Vm of 10 V, lower than Vpp and higher than 0 V, is applied to the control gate of any memory cell not selected. At the same time, 10 V is applied to the select gates SG1, and 0 V to the select gates SG2. Further, 0 V is applied to any bit line to which the memory cells into which to write data "0", whereas the intermediate voltage Vm (10 V) is applied to any bit line to which the memory cells in which to preserve data "1."
Therefore, an electric field is generated which is so intense that a tunnel current flows through the tunnel oxide film under the floating gate of a selected memory cell. A control gate of the selected memory cell is set at Vpp. Source, drain (connected to a bit line BL) and channel regions of the selected memory cell are set at 0 V. In other words, electrons are injected into the floating gate, too, raising the threshold voltage of the selected memory cell to a positive value. An electric field is applied to any memory cell not selected. However, this electric field is not intense enough to make a tunnel current flow through the tunnel oxide film of the unselected cell, because of the little difference between the write voltage Vpp (20 V) and the intermediate voltage Vm (10 V).
To read data from the NAND-type flash EEPROM, 0 V is applied to the control gate CG of any memory cell selected, and a read voltage V.sub.RD of 5 V is applied to the control gate CG of any memory cell not selected causing the unselected cell to turn on and function as a transfer gate. It is then detected whether or not a current flows through the cell from the bit line BL. The cell selected is found to store data "1" if a current flows into it, and to store data "0" if no current flows into it. A flow of a current into the cell means that the cell remains in the depleted state; no flow of a current into the cell means that the threshold voltage of the cell has risen to a positive value.
To write data into the conventional NAND-type flash EEPROM it is necessary to apply high voltage in the gate oxide film of the select transistor, i.e., the intermediate voltage Vm of 10 V. Therefore, one oxide film cannot be used as both the gate oxide film of each select transistor and the tunnel oxide film of each memory cell. That is, the gate oxide film and the tunnel oxide film need to be formed separately. Consequently, the memory cells occupy a large area, the gate oxide film and the tunnel oxide film can hardly be made to have the same or similar quality.
Moreover, to operate the conventional NAND-type flash EEPROM, three different voltages are involved, including Vpp, Vm and a read voltage V.sub.RD of 5 V. MOSFETs of three different types need to be incorporated in the circuits peripheral to the memory cell array. Particularly, MOSFETs driven by the intermediate voltage Vm must be used in the column decoder, inevitably increasing the area the column decoder occupies. Further the voltage-boosting circuit 15 comprises two types of boosting units for Vpp and Vm, resulting in occupation of a great part of the conventional NAND-type flash EEPROM.